Location: Beijing, China
Responsibilities:
RTL synthesis
Large scale Integrated Circuit Place & Route with advance technology nodes (like 40nm)
Timing analysis and fixing, timing signoff
Design for Test
Physical Signoff (DRC & LVS)
Deliver SOC chips within schedule
Qualifications:
MUST HAVE:
Have clear and good concept for digital IC design, including timing and semiconductor knowledge.
Good team-player with open-minded and proactive working style
Good communication skills in English both writing and verbal
BSEE or above in related field
NICE TO HAVE:
Experiences in EDA tools, specially Place and Route tools is a strong plus
Experiences in IC design is a strong plus
Experience in Unix/Linux working environment is a plus
Experience in TCL, Perl language is a plus
Location: Beijing, China
Responsibilities:
In this role you will participate in design and implementing structural and gate-level RTL for image signal processing in highly complex digital communication and multimedia SOC’s.
Responsibilities include micro-architecture definition, logic design, DFT and timing closure; other responsibilities may include block level verification, FPGA prototyping and image quality testing.
Qualifications:
MS degree in Electrical Engineering or Computer Science
5+ years experience in micro-architecture and RTL logic design (Verilog and/or VHDL)
3+ years experience in image signal processing
Good knowledge in image processing algorithm
Knowledge in AXI bus and ddr system
Good knowledge in design flow: Synthesis, Static Timing Analysis, Formal etc.
Good lab skills. Working knowledge of FPGA based prototyping
Strong software/algorithm skills (C/C++ programming) is desired
Strong UNIX scripting skills required, Perl/TCL/bash/csh
Excellent communication and presentation skills
Well organized, methodical, and detail oriented
Team player, and easy to work with
Location: Beijing, China
Responsibilities:
Develop embedded Video subsystem for Availink HW platform.
Improve and maintain existing software components, includes drivers. Video pipeline, multimedia middleware.
Assist with the hardware design and performance evaluation.
Qualifications:
With 3+ years of relevant working experience
Solid knowledge/experience on existing video coding technologies and standards, such as MPEG2, MPEG-AVC/H.264 and its SVC and MVC extensions
Solid knowledge on video post-processing, such as de-interlacing, scaling, framerate conversion...
Excellent understanding of the lip-syncing (A/V sync).
Experience in design & development of framework/middleware/driver & validation test bench for HW based video codec.
Experience in integration of video components with system software (Multimedia framework/middleware)
Knowledge on generic video decoder internals, video quality issues and enhancements
Hands on C Programming in embedded platforms